Once all the design schematics were in to Design Automation department (DA), it was time for another major design review using the “final” schematics. We would look for any last minute corrections, assess the status of the firmware and software, and design on our debug strategy. I knew that this was the lull before the “storm” of debug. Now the B6900 group was well funded, so they built three prototype CPU’s. This would allow them to debug on two, while the third was being reworked up to the latest logic level. We did not have that luxury. We would have one B5900 breadboard. So I had to schedule debug around the clock, which would mean my engineers would have to work in the middle of the night. The schedule was two 10 hour shifts, with one hour overlap, and two hours for rework, six days a week. The shifts were 5AM until 1PM, rework from 1PM until 3PM, and 3PM until 2AM.
So I wanted to really build up the troops, I decided to pitch the design review for Alta, Utah in November of 1978. Bill Ellis really thought I had gone nuts. No way the Erv was going to approve a three day ski design review! I informed Ron Tucker and John McClintock. They just smiled. I went to Erv with the details, he told me he had to think about it. I mentioned to him jokingly, “Erv, Piscataway is designing the B5900 memory controller, it’s only fair that we meet Ken Jensen and Bob Olson half way, and Utah is about half way between California and New Jersey!” Erv laughed. He knew the B6900 team had the luxury accommodations, three prototypes, the large lab, no late night schedule. He decided to indulge me. He approved the design review!
I remember that Bob Leamy and Gary Beck were angry. Gary told me he did not think it was fair that I got the trip to Alta. I said, “Gary, how can you complain? I am asking my engineers to work until 2AM. we have to do much of our own rework, and we have only a single prototype”. He understood but was still not happy.
We had a great design review, but mostly just had a lot of fun. The trip cemented a camaraderie between all the engineers and programmers that lasted though the project.
After our return the engineers began developing their test routines, or vectors. At that time the way machines were debugged was using test vectors. You loaded the flip-flops in the machine via a maintenance path, issued system clock, and verified if the state was as expected. While the B5900 had a lot of logic, it also had a lot of RAM in the processor itself. The DP had RAM, and the SLC was almost completely RAM. This required a totally different method of test. In the DP for example the proper way to test was to load short microcode sequences in the SLC and execute a command, then check the result. In order to load test vectors and microcode we needed a maintaince interface.